The present embodiments relate to semiconductor circuits and are more particularly directed to a Schottky diode with minimal vertical current flow.
Semiconductor devices are prevalent in all aspects of electronic circuits, and such circuits use numerous types of elements including transistors. Due to the dominance of transistors in many designs, the circuit method flows are often developed toward constructing the transistors. For this reason, other circuit elements are preferably implemented as part of the same steps as the transistor method flow. In a less desirable case, in some instances an additional step or steps to the transistor method flow are required to also construct other types of circuit elements.
Consistent with the above, another known semiconductor circuit element is a Schottky diode. A Schottky diode typically includes a metal to lightly-doped semiconductor interface, where this interface is known to have rectifying characteristics. In many applications, the semiconductor portion at this interface is created using an N type material because the resulting diode has a larger barrier height than if a P type semiconductor is used, and in many applications the larger barrier height is desirable. However, in some applications it may be desirable to have the lower barrier height as provided by a P type material included in a Schottky diode. For example, one such application is the implementation of radio frequency identification (“RFID”) devices. A passive RFID tag device, as known in that art, is a device that has no internal energy source. It receives a radio frequency (“RF”) signal and provides a corresponding current in response to that signal. In some applications, the RFID device will receive a relatively small RF signal and, hence, in these applications a low-barrier Schottky diode is desirable so as to be operable to sufficiently detect the small RF signal. In other more general applications, a disadvantage, however, may arise in low-barrier Schottky diodes in that there may be a dominance of series resistance that may cause a relatively large amount of current flow at low voltage and such current also will be affected by the series resistance. In these latter cases, therefore, the use of an N type semiconductor Schottky diode may be preferred. In any event, therefore, one skilled in the art will appreciate applications for either N type or P type semiconductor Schottky diodes.
By way of further background, semiconductor Schottky diodes have been constructed and used in the prior art and in the general form of the cross-sectional illustration of FIG. 1a, which depicts a diode 10. Diode 10 is formed in connection with a semiconductor substrate 12, which in the example of FIG. 1a is a P type semiconductor material and which is lightly-doped, as shown by the conventional designation of “P−” in FIG. 1 for such type and level of doping. For sake of explanation here and later contrast to the preferred embodiments, the majority axis of substrate 12 is shown by way of a dashed line and indicated as 12A and in the illustration is generally horizontal. A layer of N type material is formed such as an N well 14 generally above or as part of the top portion of substrate 12, and it is lightly-doped as shown by the conventional designation of “N−” in FIG. 1 for such type and level of doping. Separating at least a portion of substrate 12 from N well 14 is a buried layer 16, which is N type and heavily-doped as shown by the conventional designation of “N+” in FIG. 1 for such type and level of doping. Note that the descriptor “buried layer” is just one of various terms used in the art, so as to describe a portion of semiconductor material that is beneath the surface of an overlying layer; thus, in the example of FIG. 1, buried layer 16 is beneath the surface 14s of the overlying layer of N well 14. A buried layer such as buried layer 16 may be formed in various fashions, such as by forming it in substrate 12 prior to forming an overlying layer or, alternatively, by using a high energy implantation process that is able to penetrate surface 14s and form the layer deeper than that surface so that some unaffected and different doped level of material (e.g., N type for well 14) is left above the buried layer implant and without the dopant concentration of that buried layer. A heavily-doped conductive region 18 is formed from surface 14s down to, and of the same conductivity type as, buried layer 16; region 18 also may be referred to by various terms such as a sinker and thus hereinafter this region is referred to as sinker 18. In the present example where buried layer 16 is N+ material, then so is sinker 18. Lastly, diode 10 includes two metal-silicide regions 20 and 22. Metal-silicide region 20 is formed over and in contact with sinker 18, and metal silicide region 22 is formed along surface 14s. Note that diode 10 may include other regions or portions, but they are not illustrated so as to simplify the illustration while permitting a focus on various noteworthy aspects.
The operability of diode 10 is now discussed in connection with FIG. 1b, which again depicts diode 10 but includes a few additional illustrated aspects. As introduced earlier, a metal to lightly-doped semiconductor interface provides rectifying characteristics; thus, in diode 10, the interface of metal-silicide region 22 to N well 14 creates such characteristics. Thus, in operation, this interface performs akin to a PN junction, so a positive forward bias voltage may be applied to metal-silicide region 22 relative to metal silicide region 20. With this bias, current flows from metal-silicide region 22 to N well 14, as shown in FIG. 1b by the generally vertical dashed arrows in N well 14. Thus, with respect to this current flow, it generally is vertical and not parallel to the lateral (or horizontal) majority axis 12A of substrate 12. Also in this regard, therefore, metal-silicide region 22 operates as the diode anode, providing the direction of inward current flow. Further, the relatively lower potential at metal-silicide region 20 is connected through an ohmic connection to the relatively high doping of sinker 18, which further connects that potential to buried layer 16; thus, the current flow continues from N well 14 through buried layer 16 and sinker 18 toward metal silicide region 20, thereby permitting the latter to be referred to as the diode cathode. Given the preceding, it is observed now, and by way of contrast to the preferred embodiments detailed later, that the prior art diode 10 includes a considerable vertical component in the direction of its current flow. This vertical component occurs due to the inclusion and use of buried layer 16 as part of the diode's conductive path, whereby vertical current flow is facilitated both through well 14 to buried layer 16 and from buried layer 16 through sinker 18.
While diode 10 has proven usable and beneficial in various implementations, the present inventors have recognized that it may have certain drawbacks in some circuits. For example, some method flows may not include a buried layer of the configuration as shown in FIGS. 1a and 1b. For example, there may be no buried layer or, alternatively, the buried layer may be of a relatively low doping so as not to provide a low resistance connection to the overlying region (e.g., N well 14). Thus, in these examples, including an appropriate buried layer in order to support a diode would require additional fabrication steps, and often such additions are either undesirable or infeasible due to considerations of time, cost, and still other considerations.
In view of the above, there arises a need to address the drawbacks of the prior art, as is achieved by the preferred embodiments described below.